
//	----------- IMPORTANT -------------
//	Please don't change the follow code
//	It only be used for internal engineer
//	-----------------------------------

.Assembly	INC_VER		01
.Assembly	FPPA_NUM	1
.Assembly	RAM_Size	0x100
.Assembly	ROM_Size	0C00h
.Assembly	BOOT_TYPE	4
.Assembly	OTP_ID		2AA2h
.Assembly	LCD			PB0, PB1, PB2, PB5, PB6		//	EV ICE not support PB0

.Assembly	INSTRUMENT	SYM_86B
	.Assembly	OPTION_REG	ROP	1	Interrupt_Src0	PA.0	PB.5
	.Assembly	OPTION_REG	ROP	0	Interrupt_Src1	PB.0	PA.4
	.Assembly	OPTION_REG	ROP	6	GPC_PWM			Disable	Enable
	.Option_Help
	{
		GPC_PWM	: 	"GPC control PWM output"
	}
	.Assembly	OPTION_REG	ROP	7	PWM_Source	16MHz	32MHz
	.Assembly	OPTION_REG	ROP	5 %5	TMx_Source	16MHz	32MHz
	.Assembly	OPTION_REG	ROP	4	TMx_Bit		6BIT	7BIT

	.Assembly	OPTION	0	Security	Enable	Disable
	.Option_Help
	{
		Security	: 	"Security select"
		Enable		: 	"Security 7/8 words Enable"
		Disable		: 	"Security Disable"
	}
	.Assembly	OPTION	8	PB4_PB5_Drive	Normal	Strong
	.Assembly	OPTION	11	Bootup_Time	Slow	X	X	Fast
	.Assembly	OPTION_VIRTUAL:8	LVR		^4.5V  4.0V  X  3.5V  X  X  3.0V  2.7V  2.5V  X  X  2.2V  X  2.0V  X  1.8V
	.Assembly	OPTION_REG	MISC2	5	Comparator_Edge		All_Edge	Rising_Edge		Falling_Edge
	.Assembly	OPTION_REG	MISC2	=	0
	.Assembly	OPTION_LOW	1, 10, 15			//	Ratio:[3:1]
	.Assembly	OPTION_DEFAULT	0x7AFD
	.Assembly	OTHER_HIGH
	#pragma		Set ICE		FPGA

.Assembly	ICE_INSTR	SYM_86A
	.Assembly	OPTION_REG	@0x2A	1	Interrupt_Src0	PA.0	PB.5
	.Assembly	OPTION_REG	@0x2A	0	Interrupt_Src1	PB.0	PA.4
	.Assembly	OPTION_VIRTUAL	GPC_PWM			Disable	Enable
	.Assembly	OPTION_VIRTUAL	%7	PWM_Source	16MHz	32MHz
	.Assembly	OPTION_VIRTUAL	%5	TMx_Source	16MHz	32MHz
	.Assembly	OPTION_VIRTUAL	%4	TMx_Bit		6BIT	7BIT

	.Assembly	OPTION_VIRTUAL	Security	Enable	Disable
	.Assembly	OPTION_VIRTUAL	PB4_PB5_Drive	Normal	Strong
	.Assembly	OPTION_VIRTUAL	Bootup_Time	Slow	Fast
	.Assembly	OPTION	0		LVR	4.5V|4.0V|3.75V		3.5V|3.3V|3.15V		3.0V	2.7V	2.5V|2.4V|2.3V	1.8V	2.2V|2.1V	2.0V|1.9V
	.Assembly	OPTION	15	Comparator_Edge		All_Edge	Rising_Edge		Falling_Edge
	.Assembly	OPTION_DEFAULT	0x0047	//	Not 0x0107 : LCD
	.Assembly	OTHER_LOW

	.Assembly	RAM_Size	(-0x10)

.Assembly	ICE_INSTR	SYM_83B2
	.Assembly	OPTION_REG	OPR21	2	%1	Interrupt_Src0	PA.0	PB.5
	.Assembly	OPTION_REG	OPR21	0:1	%0	Interrupt_Src1	PB.0	PA.4

	.Assembly	OPTION_REG	GPC2PWM	@	GPC_PWM			Enable = 0xFF	Disable = 0

	.Assembly	OPTION_REG	OPR2	1	%7	PWM_Source	16MHz	32MHz
	.Assembly	OPTION_REG	OPR2	5	%5	TMx_Source	16MHz	32MHz
	.Assembly	OPTION_REG	OPR2	4	%4	TMx_Bit		6BIT	7BIT

	.Assembly	OPTION_REG	PBHD	@	PB4_PB5_Drive	Normal = 0	Strong = 0x30
	.Assembly	OPTION_VIRTUAL	Security	Enable	Disable
	.Assembly	OPTION_VIRTUAL	Bootup_Time	Slow	Fast
	.Assembly	OPTION_VIRTUAL:8	LVR	4.5V 4.0V X 3.5V X X 3.0V 2.7V 2.5V X X 2.2V X 2.0V X 1.8V
	.Assembly	OPTION_REG	OPR20	5	Comparator_Edge		All_Edge	Rising_Edge		Falling_Edge
	.Assembly	OPTION_REG	OPR20	+0x06
	.Assembly	OPTION_LOW	7 ~ 8, 12, 14	//	[9:11] Ratio	[1]:ISP
	.Assembly	OPTION_DEFAULT	0xAE7F
	.Assembly	OTHER_HIGH

	#pragma		ICE_ISP (2604)
//	PWMGxC.Enable not exist
//	RFCC not exist

.Assembly	END_INSTR

	FLAG		IO_RW		0x00
		OV	IO_RW		FLAG.3
		AC	IO_RW		FLAG.2
		CF	IO_RW		FLAG.1
		ZF	IO_RW		FLAG.0

	SP		IO_RW		0x02

	CLKMD		IO_RW		0x03
		$ 7 ~ 5, 3 :	IHRC/4, IHRC/16, IHRC/2, IHRC/8,
				X, ILRC/16, EOSC/4, IHRC/32,
				EOSC/2, IHRC/64, EOSC/1, EOSC/8,
				ILRC/4, X, ILRC/1
		$ 4	:	X, En_IHRC
		$ 2	:	X, En_ILRC
		$ 1	:	X, En_WatchDog
		$ 0	:	X, En_Reset

#if	_SYS(AT_ISP_ICE)
	INTEN		IO_RW		0x04, 0x06
		$ 9	:	X, LPWM
#else
	INTEN		IO_RW		0x04
		$ 5	:	X, PWMG0 | LPWM
#endif
		$ 7	:	X, TM3
		$ 6	:	X, TM2
		$ 4	:	X, COMP
		$ 3	:	X, AD
		$ 2	:	X, T16
		$ 1	%0	:	X, PB0 | PA4
		$ 0	%1	:	X, PA0 | PB5

#if	_SYS(AT_ISP_ICE)
	INTRQ		IO_RXW		0x05, 0x07
		$ 9	:	X, LPWM
#else
	INTRQ		IO_RXW		0x05
		$ 5	:	X, PWMG0 | LPWM
#endif
		$ 7	:	X, TM3
		$ 6	:	X, TM2
		$ 4	:	X, COMP
		$ 3	:	X, AD
		$ 2	:	X, T16
		$ 1	%0	:	X, PB0 | PA4
		$ 0	%1	:	X, PA0 | PB5

	T16M		IO_RW		0x06
		$ 7 ~ 5	:	STOP, SYSCLK, X, PA4_F, IHRC, EOSC, ILRC, PA0_F
		$ 4 ~ 3	:	/1, /4, /16, /64
		$ 2 ~ 0	:	BIT8, BIT9, BIT10, BIT11, BIT12, BIT13, BIT14, BIT15

	EOSCR		IO_WO		0x0A
		$ 7	:	Disable, Enable
		$ 6 ~ 5	:	X, 32KHZ, 1MHZ, 4MHZ	: BIT 7		//	32KHz is reserved

	INTEGS		IO_WO		0x0C
		$ 4	:	BIT_R, BIT_F
		$ 3 ~ 2	%0	:	PB0_B | PA4_B,	PB0_R | PA4_R,	PB0_F | PA4_F
		$ 1 ~ 0	%1	:	PA0_B | PB5_B,	PA0_R | PB5_R,	PA0_F | PB5_F

	PADIER		IO_WO:INIT		0x0D : 0xF9
	PBDIER		IO_WO:INIT		0x0E
	PCDIER		IO_WO:INIT		0x0F : 0x0F

	PA		IO_RW		0x10 : 0xF9
	PAC		IO_RW		0x11 : 0xF9
	PAPH		IO_RW		0x12 : 0xF9

	PB		IO_RW		0x13
	PBC		IO_RW		0x14
	PBPH		IO_RW	0x15

	PC		IO_RW		0x16 : 0x0F
	PCC		IO_RW		0x17 : 0x0F
	PCPH		IO_RW		0x18: 0x0F

	PBPL		IO_RW		0x19 : 0x0C
	PCPL		IO_RW		0x1A : 0x03

	ADCC		IO_RW		0x20
		AD_START	IO_RW		ADCC.6
		AD_DONE		IO_RW		ADCC.6

		$ 7	:	Disable, Enable
		$ 6	:	X, Go	:	WR_BIT
	#if		_SYS(AT_EV_ICE)
		$ 5 ~ 2	:	PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
				PA3, PA4, PA0, PC2 (PA1), PC1, X, X, BANDGAP
	#elif	_SYS(AT_ISP_ICE)
		$ 5 ~ 1	:	PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
					PA3, PA4, PA0, X, PC1, X, X, X,
					X, X, X, X, X, PC2, X, X,
					X, X, X, X, X, X, X, BANDGAP
	#else
		$ 5 ~ 2	:	PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
				PA3, PA4, PA0, PC1, PC2, X, X, BANDGAP
	#endif

	ADCM		IO_RW		0x21
		$ 7 ~ 5	=	4	:	12BIT
		$ 4		=	0
		$ 3 ~ 1	:	/1, /2, /4, /8, /16, /32, /64, /128

	ADCRH		IO_RO		0x22
	ADCRL		IO_RO		0x23

	ADCRGC		IO_WO		0x24	//	130524A
	#if	_SYS(AT_ISP_ICE)
		$ 7 ~ 5	:	VDD, X, X, X, PB1
		$ 4 ~ 0	=	0
	#else
		$ 7	:	VDD, PB1
	#endif

	MISC		IO_WO		0x26
		$ 6	:	EC_High_Drive, EC_Low_Drive
		$ 5	:	X, Fast_Wake_Up
		$ 4	:	X, LCD_Enable
		$ 3	=	0
		$ 2	:	X, LVR_Disable
	#if	_SYS(AT_EV)
		$ 1 ~ 0	:	WDT_X, WDT_8K | WDT_16K, WDT_64K | WDT_256K		:	1	?
	#else
		$ 1 ~ 0	:	WDT_8K, WDT_16K, WDT_64K, WDT_256K
	#endif

	MISC2		IO_WO:OP		0x27 (-)
		$ 6 ~ 5	:	Both, Rising, Falling	//	ref :	ICE_INSTR.OPTION_HIGH

	MISC_LVR		IO_WO:OP	0x28
	#if	_SYS(AT_FPGA_ICE)
		$ 7 ~ 4 :	1V8, 1V9, 2V, 2V1, 2V2, 2V3, 2V4, 2V5, 2V7, 3V | 3V15 | 3V3 | 3V5 | 3V75 | 4V | 4V5
	#else
		$ 7 ~ 4 :	1V8, 1V9, 2V, 2V1, 2V2, 2V3, 2V4, 2V5, 2V7, 3V, 3V15, 3V3, 3V5, 3V75, 4V, 4V5
	#endif
//		$ 1 ~ 0	:	BG_On, BG/4, BG/32, BG_Auto	//	221129B : Remove BG_xx

	GPCC		IO_RW		0x2B
		GPC_Out	IO_RO		GPCC.6
		$ 7	:	Disable, Enable
		$ 6	R	X, Status | Out_High
		$ 5	:	X, Sync_TM2
		$ 4	:	X, Inverse
		$ 3 ~ 1	:	N_PA3, N_PA4, BANDGAP, N_R, N_PB6, N_PB7
		$ 0	:	P_R, P_PA4

	GPCS		IO_WO		0x2C
		$ 7	:	X, Output		// Output to PA0
		$ 6	:	X, Wakeup		//
		$ 5 ~ 0	=	GPCS
		/*	At bit 5 ~ 0, you can use the follow items
				VDD*(9~24)/32
				VDD*(1~16)/24
				VDD*(9~24)/40
				VDD*(1~16)/32

                        Ex :    $ GPCS  Output, VDD*15/32
                                $ GPCS  Output, VDD/2
		*/


	TM2C		IO_RW		0x30
		$ 7 ~ 4	%5	:	STOP, SYSCLK, IHRC | IHRC*2, EOSC, ILRC, GPCRS, X, X,
				PA0_R, PA0_F, PB0_R, PB0_F, PA4_R, PA4_F
		$ 3 ~ 2	:	Disable, PB2, PA3, PB4
		$ 1	:	Period, PWM
		$ 0	:	X, Inverse

	TM2CT		IO_RW		0x31

	TM2S		IO_WO		0x32
		$ 7	%4	:	8BIT, 6BIT | 7BIT
		$ 6 ~ 5	:	/1, /4, /16, /64
		$ 4 ~ 0	=	/1 ~ /32

	TM2B		IO_WO		0x33

	TM3C		IO_RW		0x34
		$ 7 ~ 4	%5	:	STOP, SYSCLK, IHRC | IHRC*2, EOSC, ILRC, GPCRS, X, X,
				PA0_R, PA0_F, PB0_R, PB0_F, PA4_R, PA4_F
		$ 3 ~ 2	:	Disable, PB5, PB6, PB7
		$ 1	:	Period, PWM
		$ 0	:	X, Inverse

	TM3CT		IO_RW		0x35

	TM3S		IO_WO		0x36
		$ 7	%4	:	8BIT, 6BIT | 7BIT
		$ 6 ~ 5	:	/1, /4, /16, /64
		$ 4 ~ 0	=	/1 ~ /32

	TM3B		IO_WO		0x37

	LPWMG0C		IO_RW		0x40
		$ 6	R	X, Status | Out_High
		$ 5	:	X, Inverse
		$ 4 :	LPWMG0, LPWM_GEN
	#if	_SYS(AT_EV_ICE)
		$ 3 ~ 1	:	Disable | PB6, PB5, PC2, PA0, PB4
	#else
		$ 3 ~ 1	:	X | Disable, PB5, PC2, PA0, PB4, PB6
	#endif
		$ 0 :	GEN_XOR, GEN_OR

	LPWMGCLK	IO_WO		0x41
		$ 7	:	X, Enable
		$ 6 ~ 4	:	/1, /2, /4, /8, /16, /32, /64, /128
		$ 0	%7	:	SYSCLK, IHRC | IHRC*2

	LPWMG0DTH	IO_WO		0x42
	LPWMG0DTL	IO_WO		0x43 : 0xE0
	.W_LIMIT	Order	WO	LPWMG0DTL, LPWMG0DTH
	LPWMGCUBH	IO_WO		0x44
	LPWMGCUBL	IO_WO		0x45 : 0xC0

	LPWMG1C		IO_RW		0x46
		$ 6	R	X, Status | Out_High
		$ 5	:	X, Inverse
		$ 4	:	LPWMG1, LPWMG2
		$ 3 ~ 1	:	X | Disable, PB6, PC3, PA4, PB7

	LPWMG1DTH	IO_WO		0x48
	LPWMG1DTL	IO_WO		0x49 : 0xE0
	.W_LIMIT	Order	WO	LPWMG1DTL, LPWMG1DTH

	LPWMG2C		IO_RW		0x4C
		$ 6	R	X, Status | Out_High
		$ 5	:	X, Inverse
		$ 4	:	LPWMG2, Toggle | /2
		$ 3 ~ 1	:	X | Disable, PB3, PC0, PA3, PB2, PA5, PB5

	LPWMG2DTH	IO_WO		0x4E
	LPWMG2DTL	IO_WO		0x4F : 0xE0
	.W_LIMIT	Order	WO	LPWMG2DTL, LPWMG2DTH

	#pragma	REG_MAP	PWMG

	IHRCR		IO_WO		0x0B
	ILRCR		IO_WO		0x62	//	[7:4]
	BGTR		IO_RW		0x63	//	[7:3] [R:0]

	ROP		IO_WO:OP		0x67 (-)
		$ 7	:	PWM_16MHz, PWM_32MHz
		$ 6	:	PURE_PWM, GPC_PWM
		$ 5	:	TMx_16MHz, TMx_32MHz
		$ 4	:	TMx_6BIT, TMx_7BIT
		$ 1	:	INT_PA0, INT_PB5
		$ 0	:	INT_PB0, INT_PA4

#if	_SYS(AT_ISP_ICE)
	.include	AT_ISP_ICE.INC
#endif


/*
	ICE not support
		RAM Size = 0xF0
		RFCC :	Only support R_TYPE
		CLKMD.ILRC/16
		PBPL / PCPL
		LPWMG0C.PB6
		LPWMG2C.PA5, PB5
		LPWGG0C.LPWMG0, LPWM_GEN
		LPWGG0C.GEN_XOR/GEN_OR
		LPWMG1C.LPWMG1/LPWMG2
		LPWMG2C.PA5/Toggle
		LPWMGCLK
		ROP.PWM_xxx/TMx_xxx
		LCD.PB0 = 1/2 Bias
		TMxS.7BIT
		X_Source.32MHz

  	ICE bug
		when use ADCRGC.PB1, PA1 must float
		when use RFCC.C_Type, PA1 must float
		when use GPCC.Output, PA3 will be affect

	ICE not match IC
		MISC.Fast_Wake_Up
		MISC.WT_Txx
		PWMGx/TMxC.IHRC at ICE:16MHz
		IC:ROP.PWM_xxMHz / GPC_PWM / TMx_xxMHz / TMx_xBIT
		ADCM always 12BIT
		PCDIER
*/